Radio circuit diagrams electronics projects

Using LM111 voltage comparator , LM101 operational amplifier and some other electronic parts , can be designed a very simple and efficiency voltage controlled oscillator .

Using the AD9834 75 MHz low power DDS device capable of producing high performance sine and triangular outputs.
AD9834 has an on-board comparator that allows a square wave to be produced for clock generation. Consuming only 20 mW of power at 3 V makes the AD9834 an ideal candidate for power-sensitive applications.
Capability for phase modulation and frequency modulation is provided. The frequency registers are 28 bits; with a 75 MHz clock rate, resolution of 0.28 Hz can be achieved. Similarly, with a 1 MHz clock rate, the AD9834 can be tuned to 0.004 Hz resolution. Frequency and phase modulation are affected by loading registers through the serial interface and toggling the registers using software or the FSELECT pin and PSELECT pin, respectively.
The AD9834 is written to using a 3-wire serial interface. This serial interface operates at clock rates up to 40 MHz and is compatible with DSP and microcontroller standards.
The DDS electronic project operates with a power supply from 2.3 V to 5.5 V DC. The analog and digital sections are independent and can be run from different power supplies, for example, AVDD can equal 5 V with DVDD equal to 3 V.

A low-pass filter is generally placed between the output of the DAC and the input of the comparator to further suppress the effects of aliased images.
One of the areas where the AD9834 is suitable is in modulation applications. The part can be used to perform simple modulation such as FSK. More complex modulation schemes such as GMSK and QPSK can also be implemented using the AD9834.

In an FSK application, the two frequency registers of the AD9834 are loaded with different values. One frequency represents the space frequency, and the other represents the mark frequency. The digital data stream is fed to the FSELECT pin, causing the AD9834 to modulate the carrier frequency between the two values.

The AD9834 has two phase registers, enabling the part to perform PSK. With phase shift keying, the carrier frequency is phase shifted, the phase being altered by an amount that is related to the bit stream that is input to the modulator.
The AD9834 is also suitable for signal generator applications. With the on-board comparator, the device can be used to generate a square wave.

Using this evaluation board of the AD9834 DDS IC you can easy program this chip for the application you need , using software from analog website .

Using ADF4007 high frequency divider PLL synthesizer can be designed a variety of communications applications. It can operate to 7.5 GHz on the RF side and to 120 MHz at the PFD. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, and a divider prescaler. The divider prescaler value can be set by two external control pins to one of four values (8, 16, 32, or 64). The reference divider is permanently set to 2, allowing an external REFIN frequency of up to 240 MHz.

A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and a VCO (voltage controlled oscillator).
This Local Oscillator electronic project use the ADF4007 with the HMC358MS8G VCO from Hittite Microwave Corporation to produce a fixed-frequency LO (local oscillator), which could be used in satellite or CATV applications. In this case, the desired LO is 6.7 GHz.
The reference input signal is applied to the circuit at FREFIN and, in this case, is terminated in 50 Ω.

To bias the REFIN pin at AVDD/2, ac coupling is used. The value of the coupling capacitor used depends on the input frequency. The equivalent impedance at the input frequency should be less than 10 Ω. Given that the dc input impedance at the REFIN pin is 100 kΩ, less than 0.1% of the signal is lost.

The charge pump output of the ADF4007 drives the loop filter. In calculating the loop filter component values, a number of items need to be considered. In this example, the loop filter was designed so that the overall phase margin for the system is 45°.
Other PLL system specifications are as follows:
KD = 5 mA KV = 100 MHz/V Loop Bandwidth = 300 kHz FPFD = 106 MHz N = 64 .
The local oscillator circuit gives a typical phase noise performance of −100 dBc/Hz at 10 kHz offset from the carrier.