Frequency doubler circuit with transistors

This frequency doubler circuit, can be viewed in two ways:
input signals> 1V
input signals <1V
When the input signal is> the 1V T2 and T3 works as rectifier, meaning it fundamental frequency of the input signal is automatically doubled.
The input signals <1V two T1 signals in antiphase products of the input signal is brought in emitters of T2 and T3 and summed. This means that virtually disappears fundamental frequency, so that, due to nonlinearities, remain only harmonics: first harmonic is now fundamental frequency output signal.
Thus resulting in a considerable attenuation of the input signal: a signal input of 25 mV remain only 6 mV output.

Assuming a sinusoidal input signal, the fundamental frequency rejection is optimized by P1. T3's operating point will be adjusted by the P2 for an output signal as close to a sinusoidal. Input frequency range extends from 80 Hz to above the 100 kHz frequency. Any tendency of T2 or T3 oscillation can be suppressed by sticking a small ceramic capacitor (about 56 pF) between the base and collector of the transistor.