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Electronic alarm with delayed trigger

An alarm with delayed trigger can be made using electronic scheme below. This electronic alarm becomes operational after about 30 after the input becomes 0 emitting four sounds at one second interval. This operation is repeated every thirty seconds until the input signal reaches a logic state 1 again.
The circuit is realized with binary counters with 14 stages, with oscillator built realized in CMOS technology type 4060. Oscillator frequency, f is determined by following formula f = 1/4R3C1, where f is in Hz, in ohms R3 and C1 in farads.
Internal oscillator is connected to the counter clock input. Once the reset input (pin 12) is in logic state 0, counter starts working. Since the initial state outputs Q4, Q7 and Q10 are in logic state 0 pin 12 will receive a low potential when N1's entry is 0. After about 30 seconds, Q10 becomes 1. Frequency of 1 Hz signal from Q4 is then applied to the base of T1. This transistor will result in the rate of 1 Hz and connect / disconnect ring with the same frequency. After four seconds, the output Q7 (pin 6) is also logic 1. Since both inputs of NAND gate N3 are now in a logical potential, output to become 0. This level will cause the reset input (pin 12) of IC2 to pass in a logical condition 1 which will reset all outputs. If the input circuit remains in a logical state 1process is resumed, otherwise, the circuit does not occur.

Circuit Diagram: 
Electronic alarm with delayed trigger circuit diagram

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